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.... ...... .... .... .... 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI3B4010 3.3V, High-Bandwidth, 40:10-Bit DDR Mux/Demux NanoSwitchTM Product Features * * * * * * RON is 35 ohms max. Standard Operating Temperature: 0C to +70C Channel ON Capacitance: 15pF max. VCC Operating Range: +3.0V to +3.6V Fast switching time: 3ns max. Package options include: - 64-ball Thin Fine Pitch Ball Grid Array (TFBGA) Product Description Pericom Semiconductor's PI3B series of logic circuits are produced using the Company's advanced submicron CMOS technology, achieving industry-leading performance. The PI3B4010 is a 3.3V, 10- to 40-bit demultiplexing/multiplexing bus switch. It is intended for multiple data or address muxing. Industry leading advantages include a propagation delay of 300ps, resulting from the 35-ohm channel resistance, and low I/O capacitance. The A-port multiplexes to one of four or all outputs allowing a complete bank of 10 bits to switch. The switch is bidirectional. Applications * DDR DIMM bank switching Logic Block Diagram Expanded Block Diagram 10 A0 0B0 1B0 2B0 A0 10 0B0 10 A1 3B0 0B 1 1B1 2B1 1B0 0B9 2B0 1B9 A2 10 3B1 0B 2 1B2 2B2 3B2 0B 3 1B3 2B3 3B3 0B 4 1B4 2B4 3B4 0B 5 1B5 2B5 3B5 0B 6 1B6 2B6 3B6 0B 7 1B7 2B7 3B7 0B 8 1B8 2B8 3B8 0B 9 1B9 2B9 3B9 A9 3B0 2B9 A3 10 SEL0 SEL1 SEL2 SEL3 A 3B9 A4 10 A5 B 10 A6 SEL 10 A7 10 A8 10 A9 10 SEL0 SEL1 SEL2 SEL3 1 PS8571A 12/11/02 321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI3B4010 3.3V, High Bandwidth, 40:10-Bit, DDR Mux/Demux NanoSwitch Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................................. -65C to +150C Supply Voltage Range ................................................ -0.5V to +4.6V DC Input Voltage .......................................................... -0.5V to +4.6V DC Output Current .................................................................... 120mA Power Dissipation ........................................................................ 0.5W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Product Pinout by Location on Connection Diagram 1 A NC 2 3 4 5 1B0 Product Pin Description Pin Name AN NB0 6 2B0 7 3B0 8 9 2B1 10 3B1 11 0B2 De s cription Demux Input Pins Mux Input Pins Bank Select Pins (Active LOW) Ground Power SEL1 VDD SEL0 GND B SEL2 NC C D E F G H J K L 1B8 2B9 0B0 Ao 0B1 1B1 A1 GND A2 3B2 1B2 VDD SEL3 GND 3B9 2B2 - NB9 SELN GND VDD 0B3 1B3 Note: N = 0 through 3 for each set of 10 Bits 1B9 A9 3B8 A3 GND 0B4 2B3 Truth Table Function SEL0 SEL1 SEL2 SEL3 L H H H H L H H H H H L H H H H H L H 0B9 3B3 2B8 Connect AN to 0BN Connect AN to 1BN 1B4 A8 GND 2B7 A4 A7 1B7 0B7 3B6 Connect AN to 2BN Connect AN to 3BN 0BN, 1BN, 2BN, 3BN 0B8 A6 1B6 GND 0B6 3B5 A5 2B5 3B4 2B4 3B7 2B6 1B5 0B5 = Pulldown, AN = Hi- Z H NC = No Connection Top View 2 PS8571A 12/11/02 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI3B4010 3.3V, High Bandwidth, 40:10-Bit, DDR Mux/Demux NanoSwitch DC Electrical Characteristics over Operating Range (TA = 0C to 70C, VCC = 3.3V 5%) Parame te r VIH VIL VIK IIH IIL RON RFLAT(ON) RON RPD De s cription Input HIGH Voltage Input LOW Voltage Clamp Diode Voltage Input HIGH Current Input LOW Current Switch On Resistance(3) On Resistance Flatness(4) On Resistance match from center ports to any other port(4) Pull- Down Resistance Te s t Conditions (1) Guaranteed HIGH Level Guaranteed HIGH Level VCC = Max., VIN = -18mA VCC = Max., VIN = VCC VCC = Max., VIN = GND VCC = Min., 0.8V VIN 2.5V, IIN = -20mA VCC = Min., VIN@0.8V and 1.7V IIN = -20mA VCC = Min., 0.8V VIN 2.5V, IIN = -20mA VIN = 0V to 2.5V M in. 1.6 -0.3 - - - - - - 80 Typ.(2) - - -0.7 - - 25 1.0 0.9 100 M ax. VCC +0.3 0.9 -1.2 10 10 35 - 2 130 A V Units Capacitance (TA = 25C, f = 1 MHz) Parame te rs CIN COFF(A) CON(A/B) COFF(B) De s cription Input Capacitance Port A Capacitance, Switch OFF A/B Capacitance, Switch ON Port B Capacitance, Switch OFF VIN = 0V Te s t Conditions Typ.(4) 3.5 12.0 15 . 0 4.5 M ax. - - - - pF Units Notes: 1. For min. or max. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, TA = 25C ambient and maximum loading. 3. Measured by the voltage drop between A and B pins at indicated current through the switch. ON resistance is determined by the lower of the voltages on the two (A & B) pins. 4. This parameter is determined by device characterization but is not production tested. Power Supply Characteristics Parame te rs ICC De s cription Quiscent Power Supply Current Te s t Conditions (1) VCC = Max., VIN = GND or VCC M in. - Typ.(2) - M ax. 10 Units A Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input (control inputs only); A and B pins do not contribute to ICC. 3 PS8571A 12/11/02 321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI3B4010 3.3V, High Bandwidth, 40:10-Bit, DDR Mux/Demux NanoSwitch Switching Characteristics (over operating range over recommended operating free-air temperature range). Parame te r tIY tSY tPZL tPLZ tSK(o) tSK(p) De s cription Propagation Delay(2,3) AN to BN w/ZO = 50 Ohms Bus Select Time - SELN to AN, BN Bus Enable Time - SELN to AN, BN Bus Disable Time - SELN to AN, BN Output skew between center ports (A4 & A5) to any other port(2) Skew between opposite transitions of the same output (ItPHL - tPLHI) (2) Conditions - - - - - - Com M in. - 0.5 0.5 0.5 - - Typ 0.3 - - - 0.1 0.1 M a x. - 3.0 3.0 3.0 0.2 0.2 Units ns Notes: 1. See test circuit and waveforms. 2. This parameter is guaranteed by design. 3. The bus switch contributes no propagational delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.75ns for 50pF load. Since this time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. Test Circuits for All Outputs(1) 5.0V VCC Switch Positions Te s t Disable LOW, Enable LOW (output on A side) 500 Switch 5.0V GND Open Disable HIGH, Enable HIGH (output on A side) Disable/Enable High (output on B side) & Prop Delay Pulse Generator VIN 55 D.U.T RT VOUT 55 8pF CL 500 Notes: 1. CL = Load capacitance: includes jig and probe capacitance. 2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator 3. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. All input impulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50, tR 2.5ns, tF 2.5ns. 5. The outputs are measured one at a time with one transition per measurement. 4 PS8571A 12/11/02 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI3B4010 3.3V, High Bandwidth, 40:10-Bit, DDR Mux/Demux NanoSwitch Switching Waveforms SEL 1.25V 1.25V 0V 2.5V 2.5V Input tPLH 1.25V 1.25V 0V tPHL VOH Output 1.25V 1.25V VOL Output A Output A tPZL 1.25V tPZH 1.25V tPZH 1.25V tPLZ VOL +0.15V tPHZ VOH -0.15V tPHZ 1.25V 2.5V VOL VOH 0V VOH 0V Output B Voltage Waveforms Propagation Delay Times Voltage Waveforms Enable and Disable Times 2.5V 1.25V Data In at Ax or Ay 0V tPLHX tPHLX VOH 1.25V Data Out at MBx I VOL tSK(o) VOH 1.25V Data Out at MBy tPLHy tPHLy tSK(o) = I tPLHy - tPLHx I or I tPHLy - tPHLx I VOL tSK(p) = I tPHL - tPLH I Output Input 0V tPLH tPHL VOH 1.25V VOL 2.5V 1.25V Output Skew - tSK(o) Pulse Skew - tSK(p) 5 PS8571A 12/11/02 0.10 0.08 321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI3B4010 3.3V, High Bandwidth, 40:10-Bit, DDR Mux/Demux NanoSwitch 64-Pin TFBGA Package .197 5.0 BSC .276 7.0 BSC. .197 5.0 BSC .020 0.5 BSC. .276 7.0 BSC. Pin #1 Corner Pin #1 Corner BOTTOM VIEW .011 .015 0.28 0.38 .007 .011 0.18 0.28 .030 0.77 MAX TOP VIEW .043 1.10 MAX Ordering Information Part PI3B4010NC Pin - Package 64 - TFBGA Applications Information Logic Inputs The logic control inputs can be driven up to +3.6V regardless of the supply voltage. For example, given a + 3.3V supply, IN may be driven low to 0V and high to 3.6V. Driving IN Rail-to-Rail(R) minimizes power consumption. Power-Supply Sequencing and Hot-Plug Information Proper power-supply sequencing is recommended for all CMOS devices. Always apply VCC and GND before applying signals to input/output or control pins. Rail-to-Rail is a registeredtrademark of Nippon Motorola, Ltd. Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 6 PS8571A 12/11/02 |
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